Semiconductor device and method for manufacturing semiconductor device

ABSTRACT

A semiconductor device of the present invention includes a semiconductor layer, a gate trench that defines a source region of a first conductivity type in the semiconductor layer, a channel region of a second conductivity type of a lower part of the source region, a source trench that passes through the source region and the channel region, an impurity region of the second conductivity type of a bottom part and a side part of the source trench, a source electrode on the semiconductor layer, and a highly-concentrated impurity region of the second conductivity type, the highly-concentrated impurity region having a contact portion connected to the source electrode at a surface of the semiconductor layer, the highly-concentrated impurity region passing through the source region and extending to a position deeper than the source region, the highly-concentrated impurity region having a concentration higher than the impurity region.

TECHNICAL FIELD

The present invention relates to a semiconductor device that has atrench gate structure, and relates to a method for manufacturing thesemiconductor device.

BACKGROUND ART

For example, Patent Document 1 discloses a power MOSFET that includes asemiconductor substrate forming a drain, a trench formed at a surface ofthe semiconductor substrate, a gate electrode formed in the trenchthrough a gate insulating film, a body diffusion layer formed on thesurface side of the semiconductor substrate, a source diffusion layerformed at the surface of the semiconductor substrate, an interlayerinsulating film formed on the gate electrode, a source electrode filmformed on the semiconductor substrate, a source trench that is formedapart from the trench, and a p type contact diffusion layer formed at abottom surface of a source trench.

PRIOR ART DOCUMENTS Patent Literature

Patent Document 1: Japanese Patent Application Publication No.2008-98593

SUMMARY OF THE INVENTION Technical Problem

One preferred embodiment of the present invention provides asemiconductor device capable of restraining variation in gate thresholdvoltage in a transistor structure that has a source trench passingthrough a source region and a channel region and that additionally hasan impurity region of a second conductivity type at a bottom part and aside part of the trench, and provides a method for manufacturing thesemiconductor device.

Solution to Problem

One preferred embodiment of the present invention provides asemiconductor device including a semiconductor layer, a gate trench thatdefines a source region of a first conductivity type in thesemiconductor layer, a channel region of a second conductivity type of alower part of the source region, a source trench that passes through thesource region and the channel region, an impurity region of the secondconductivity type of a bottom part and a side part of the source trench,a source electrode on the semiconductor layer, and a highly-concentratedimpurity region of the second conductivity type that has a contactportion connected to the source electrode at a surface of thesemiconductor layer and that passes through the source region andextends to a position deeper than the source region and that has aconcentration higher than the impurity region.

According to this arrangement, it is possible to use thehighly-concentrated impurity region as electric-charge path to thechannel region. It is possible to restrain variation in gate thresholdvoltage by using the region that is lower in resistance than impurityregion of the bottom part and the side part of the source trench as anelectric-charge path. As a result, it is possible to restrain variationin ΔVth between chips in a semiconductor wafer plane, and therefore, ifa module is formed by use of a plurality of chips that are individualpieces created from a semiconductor wafer in which the thus formedstructure has been employed, it is possible to reduce a switching timelag in the module.

In one preferred embodiment of the present invention, the source trenchmay be formed as a single source trench or as two source trenches in acutting plane that appears when the semiconductor layer is cut in adirection of a depth of the source trench.

In one preferred embodiment of the present invention, thehighly-concentrated impurity region is formed apart from a channelportion located on a side surface of the gate trench. In this case, thehighly-concentrated impurity region may be formed along a side surfaceof the source trench.

According to this arrangement, it is possible to restrain a rise in gatethreshold voltage, and it is possible to obtain a low on-resistance.

In one preferred embodiment of the present invention, thehighly-concentrated impurity region is formed so as to extend to abottom surface of the source trench.

According to this arrangement, it is possible to reduce the sheetresistance of the impurity region of a bottom part of the source trench,and therefore it is possible to reduce the resistance of a body diodeformed by the pn junction between the impurity region and a drain regionof the semiconductor layer.

In one preferred embodiment of the present invention, the contactportion is selectively formed at a part of the source region.

According to this arrangement, it is possible to widely secure a contactregion with respect to the source region in the surface of thesemiconductor layer while it is possible to connect the source electrodeto a highly-concentrated impurity region (contact portion) required tomake the channel region and the source region equal in electricpotential to each other. Therefore, it is possible to restrain a rise insource contact resistance.

In one preferred embodiment of the present invention, thehighly-concentrated impurity region is formed along an inner surface ofthe source trench so as to extend to a bottom surface of the sourcetrench, and the contact portion is selectively formed at a part of thesource region.

According to this arrangement, it is possible to reduce the sheetresistance of the impurity region of a bottom part of the source trench,and therefore it is possible to reduce the resistance of a body diodeformed by the pn junction between the impurity region and a drain regionof the semiconductor layer. Additionally, it is possible to widelysecure a contact region with respect to the source region in the surfaceof the semiconductor layer while it is possible to connect the sourceelectrode to a highly-concentrated impurity region (contact portion)required to make the channel region and the source region equal inelectric potential to each other. Therefore, it is possible to restraina rise in source contact resistance.

In one preferred embodiment of the present invention, the contactportion is formed so as to extend in at least two directions from anupper side of the source trench. In this arrangement, if the gate trenchis formed in a grid-shaped manner, the source trench may be formed in aquadrangle or a quadrangular ring shape in a plan view in an innerregion of the gate trench formed in the grid-shaped manner, and thecontact portion may be formed so as to extend outwardly from four sidesof the source trench.

According to this arrangement, it is possible to reliably form at leastother contact portions even if the mask positionally deviates in onedirection, for example, when a highly-concentrated impurity region isformed by ion implantation.

In one preferred embodiment of the present invention, a repeated patternof a line-and-space shape may be formed by the gate trench and thesource trench, or a repeated pattern of a hexagon may be formed by thegate trench.

In one preferred embodiment of the present invention, thehighly-concentrated impurity region includes a second contact portionformed at a part of the bottom part of the source trench, and thesemiconductor device may include an electrode-film residue disposed at aperipheral part of the bottom part of the source trench.

In one preferred embodiment of the present invention, the electrode-filmresidue may be formed so as to selectively cover a peripheral edge partof the second contact portion.

In one preferred embodiment of the present invention, thehighly-concentrated impurity region includes a second contact portionformed at at-least one part of a peripheral part of the source trench,and the semiconductor device may include an electrode-film residuedisposed in the source trench.

In one preferred embodiment of the present invention, the source trenchis formed in a ring shape, and the semiconductor device includes aconvex portion formed in an inner region of the source trench formed inthe ring shape, and the second contact portion is formed at a surfacepart of the convex portion.

In one preferred embodiment of the present invention, the source trenchis formed in a stripe manner, and the semiconductor device includes aconvex portion formed between the source trench and the source trenchboth of which are adjacent to each other, and the second contact portionmay be formed at a surface part of the convex portion.

In one preferred embodiment of the present invention, the electrode-filmresidue may be embedded in the source trench.

In one preferred embodiment of the present invention, the source trenchmay have a depth equal to a depth of the gate trench, and, meanwhile,may have a width greater than a width of the gate trench.

A method for manufacturing a semiconductor device of the presentinvention provides a semiconductor-device manufacturing method thatincludes a step of forming a source region of a first conductivity typeand a channel region of a second conductivity type in order from asurface of a semiconductor layer, a step of forming a gate trench thatdefines the source region so as to have a predetermined shape and asource trench located in the source region, a step of forming animpurity region at a bottom part and a side part of the source trench byimplanting an impurity of the second conductivity type into the sourcetrench in a state in which a surface of the source region is masked, anda step of forming a highly-concentrated impurity region, which passesthrough the source region and extends to a position deeper than thesource region and which has a concentration higher than the impurityregion, by implanting an impurity of the second conductivity type in astate in which the surface of the source region is partially masked.

This method makes it possible to manufacture a semiconductor deviceaccording to one preferred embodiment of the present invention.

In one preferred embodiment of the present invention, the step offorming the highly-concentrated impurity region includes a step ofdiagonally implanting the impurity of the second conductivity type intoa side surface of the source trench by use of a mask that exposes aninside of the source trench.

This method makes it possible to form a highly-concentrated impurityregion along the side surface of the source trench withoutdisconnection.

In one preferred embodiment of the present invention, the step offorming the highly-concentrated impurity region includes a step ofimplanting an impurity under a condition of being higher in dose amountand lower in energy than when the impurity region is formed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view of a semiconductor device according toone preferred embodiment of the present invention.

FIG. 2 is a view to describe one preferred embodiment of thesemiconductor device.

FIG. 3 is a flowchart to describe a method for manufacturing thesemiconductor device.

FIG. 4 is a view to describe the step that forms the p type region.

FIG. 5 is a view to describe a step of forming a p⁺ type channel contactregion.

FIG. 6 is a view to describe one preferred embodiment of thesemiconductor device.

FIG. 7 is a view to describe a step of forming a p type region.

FIG. 8 is a view to describe a step of forming a p⁺ type channel contactregion.

FIG. 9 is a view to describe one preferred embodiment of thesemiconductor device.

FIG. 10 is a view to describe one preferred embodiment of thesemiconductor device.

FIG. 11 is a view to describe a variation improvement effect of ΔVth.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be hereinafterdescribed in detail with reference to the accompanying drawings.

FIG. 1 is a schematic plan view of a semiconductor device 1 according toone preferred embodiment of the present invention.

The semiconductor device 1 includes a power MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor) element (discreteelement) that uses SiC (silicon carbide). For example, the length in theup-down direction of the semiconductor device 1 in the sheet of FIG. 1is about 1 mm.

The semiconductor device 1 includes a SiC substrate 2 as an example of asemiconductor layer. The SiC substrate 2 is composed of an activeportion 3 that is disposed at its central part and that functions as afield-effect transistor and an outer peripheral portion 4 that surroundsthe active portion 3.

A source electrode 5 made of, for example, aluminum is formed so as tocover substantially the whole area of the active portion 3. The sourceelectrode 5 has a substantially square shape in a plan view. A removalregion 6 that surrounds a central part of the source electrode 5 alongthe outer peripheral portion 4 is formed at a peripheral edge of thesource electrode 5. The removal region 6 has its part selectivelyhollowed toward the central part of the source electrode 5. A gate pad 7is placed at this hollowed part. A gate finger 8 made of, for example,aluminum extends over the entire removal region 6 from the gate pad 7along the outer peripheral portion 4. A pair of gate fingers 8 areformed in a symmetrical shape with respect to the gate pad 7.

A gate trench 9 is formed in the SiC substrate 2 directly under thesource electrode 5 etc. The gate trench 9 is formed at the activeportion 3. The gate trench 9 is formed in a grid-shaped manner. Thepattern of the gate trench 9 is not limited to that of the grid-shapedmanner. For example, the gate trench 9 may be formed in a stripe-shapedmanner or a honeycomb-shaped manner.

The active portion 3 is partitioned into a larger number of unit cells10 by means of the gate trench 9. In the active portion 3, many unitcells 10 are regularly arrayed in a matrix manner (columns-and-rowsmanner). An n⁺ type source region 11 (for example, a concentration of1×10¹⁸ cm⁻³ to 5×10²¹ cm⁻³) is formed at an upper surface of each unitcell 10, and a p type channel region 12 (for example, a concentration of1×10¹⁶ cm⁻³ to 1×10¹⁹ cm⁻³) is formed at a lower part thereof.

A source trench 13 is formed in each unit cell 10. The source trench 13passes through the n⁺ type source region 11 and the p type channelregion 12. The source trench 13 may have a shape defined by only outerperipheral sides in a plan view (part on the upper side of FIG. 1). Inthis case, in a cutting plane that appears when the SiC substrate 2 iscut in its depth direction, one source trench 13 appears as shown by across section along line A-A (first pattern of the source trench 13). Indetail, as shown in FIG. 1, it may be a (regular) quadrangle, a(regular) hexagon, a circle, or the like in a plan view. On the otherhand, the source trench 13 may have a shape defined by both sides, i.e.,by both the outer peripheral sides and inner peripheral sides in a planview (part on the lower side of FIG. 1). In this case, in a cuttingplane that appears when the SiC substrate 2 is cut in its depthdirection, two source trenches 13 appear as shown by a cross sectionalong line B-B (second pattern of the source trench 13). In detail, asshown in FIG. 1, it may be a (regular) quadrangular ring shape, a(regular) hexagonal ring shape, a circular ring shape, or the like in aplan view. It should be noted that the shape of the source trench 13mentioned above is merely one example, and the source trench 13 may haveanother shape.

In the outer peripheral portion 4, the gate finger 8 is formed so as tosurround the source electrode 5.

Next, a structure of the semiconductor device 1 will be described indetail. FIG. 2 is a view that shows one preferred embodiment of thesemiconductor device 1 in detail, in which the source trench 13 has thefirst pattern.

The SiC substrate 2 may be a SiC epitaxial substrate that includes an n⁺type base substrate 14 (for example, a concentration of 1×10¹⁸ cm⁻³ to5×10²¹ cm⁻³) and an n⁻ type active layer 15 (for example, aconcentration of 1×10¹⁴ cm⁻³ to 1×10¹⁷ cm⁻³) that has been generated byepitaxial growth thereon.

The gate trench 9 is formed in the n⁻ type active layer 15. The gatetrench 9 is formed in a grid-shaped manner. The gate trench 9 integrallyincludes a side surface 16, a bottom surface 17, and a corner portion 18that is an intersection portion between the side surface 16 and thebottom surface 17. The gate trench 9 is formed in the shape of theletter U in cross section so that the corner portion 18 becomes a curvedplane.

A gate insulating film 19 is formed at the inner surface (the sidesurface 16, the bottom surface 17, and the corner portion 18) of thegate trench 9. The gate insulating film 19 covers the whole area of theinner surface, and covers an upper-end peripheral edge of the unit cell10. The gate insulating film 19 is made of, for example, an insulatingmaterial, such as silicon oxide (SiO₂).

A gate electrode 20 is embedded in the gate trench 9. The gate electrode20 is made of, for example, a conductive material, such as polysilicon.

The source trench 13 is formed at a central part of each unit cell 10.The source trench 13 has the same depth as the gate trench 9, and, onthe other hand, has a width larger than the gate trench 9. The sourcetrench 13 integrally includes a side surface 21, a bottom surface 22,and a corner portion 23 that is an intersection portion between the sidesurface 21 and the bottom surface 22. The source trench 13 is formed inthe shape of the letter U in cross section so that the corner portion 23becomes a curved plane. An insulating-film residue 24 and anelectrode-film residue 25 remain at a lower part of the source trench13. The insulating-film residue 24 is selectively present at the cornerportion 23 and around the corner portion 23 so as to expose a centralpart of the bottom surface 22. The electrode-film residue 25 is presentonly on the insulating-film residue 24. In other words, the flat surfacepattern of the insulating-film residue 24 and that of the electrode-filmresidue 25 match each other.

The n⁺ type source region 11, the p type channel region 12, and an n⁻type drain region 26 are formed in this order at each unit cell 10 fromthe front surface of the n⁻ type active layer 15 toward the reversesurface thereof. These regions 11, 12, and 26 are contiguous to eachother. The n⁻ type drain region 26 is a part of the n⁻ type active layer15 that is positionally lower than the p type channel region 12. Atrench-gate type MOS transistor structure is thus formed in which the n⁺type source region 11 and the n⁻ type drain region 26 are disposed apartfrom each other through the p type channel region 12 in the verticaldirection perpendicular to a front surface of the SiC substrate 2.

The n⁺ type source region 11 forms a part of the side surface 16 of thegate trench 9 and a part of the side surface 21 of the source trench 13.Likewise, the p type channel region 12 forms a part of the side surface16 of the gate trench 9 and a part of the side surface 21 of the sourcetrench 13. The n⁻ type drain region 26 forms the corner portion 18 andthe bottom surface 17 of the gate trench 9 and the corner portion 23 andthe bottom surface 22 of the source trench 13.

A p type region 27 is formed at the n⁻ type active layer 15 (forexample, a concentration of 1×10¹⁶ cm⁻³ to 1×10¹⁹ cm⁻³). The p typeregion 27 has a concentration higher than the p type channel region 12.The p type region 27 is formed at a substantially constant thicknessalong the inner surface of the source trench 13. The p type region 27has an outer surface that extends in the vertical direction along theside surface 21 from the p type channel region 12 and that extends inthe lateral direction along the bottom surface 22. The outer surface onthe longitudinal side of the p type region 27 is disposed apart inwardlyfrom the gate trench 9. Therefore, the n− type drain region 26 and the ptype channel region 12 connected to the p type region 27 are present inan intermediate region between the outer surface and the gate trench 9.The thickness of the p type region 27 (depth in the lateral directionfrom the side surface 21 or depth in the longitudinal direction from thebottom surface 22) is, for example, 0.4 μm to 1.5 μm.

A p⁺ type channel contact region 28 is further formed at the n⁻ typeactive layer 15 (for example, a concentration of 1×10¹⁸ cm⁻³ to 5×10²¹cm⁻³). The p⁺ type channel contact region 28 has a concentration higherthan the p type channel region 12 and the p type region 27. The p⁺ typechannel contact region 28 integrally includes a first contact portion29, a longitudinal extension portion 30, and a second contact portion31.

The first contact portion 29 is selectively formed at a part of theouter peripheral portion (n⁺ type source region 11) that surrounds thesource trench 13. In the present preferred embodiment, it is formed soas to extend outwardly from central parts of four sides of thequadrangular source trench 13 in a plan view. An arrangement is formedsuch that the first contact portion 29 is formed at only a part of theouter peripheral portion of the source trench 13, and therefore it ispossible to widely secure a contact region with respect to the n⁺ typesource region 11 in the front surface of the SiC substrate 2 while it ispossible to connect the source electrode 5 to the p⁺ type channelcontact region 28. Therefore, it is possible to restrain a rise insource contact resistance. A forward end of the first contact portion 29is disposed apart inwardly from the gate trench 9. As a result, the n⁺type source region 11 having a predetermined width is secured betweenthe forward end of the first contact portion 29 and the gate trench 9,and therefore, likewise, in this position, it is possible toelectrically connect the source electrode 5 to the n⁺ type source region11. In the present preferred embodiment, the forward end of the firstcontact portion 29 is further disposed on an inner side than the outersurface on the longitudinal side of the p type region 27. Additionally,the thickness of the first contact portion 29 (depth in the longitudinaldirection from the front surface of the n⁻ type active layer 15) is 0.1μm to 0.3 μm.

The longitudinal extension portion 30 extends from the first contactportion 29 to a position deeper than the n⁺ type source region 11, andfaces the p type channel region 12 beside the gate trench 9. Thelongitudinal extension portion 30 extends along the inner surface of thesource trench 13 with substantially the same width as the first contactportion 29, and is connected to the second contact portion 31 in acentral part of a region surrounded by the outer peripheral sides of thesource trench 13. The longitudinal extension portion 30 is exposed tothe inner surface of the source trench 13, and, on the other hand, isdisposed apart inwardly from the gate trench 9. This makes it possibleto prevent the longitudinal extension portion 30 from being formed inthe p type channel region 12 (part in which a channel is formed) on theside surface 16, and hence makes it possible to restrain a rise in gatethreshold voltage, and makes it possible to obtain a low on-resistance.The first contact portion 29 is arranged as a drawn portion drawnoutwardly from the longitudinal extension portion 30 in an upper part ofthe source trench 13. Additionally, the thickness (depth in the lateraldirection from the side surface 21 of the source trench 13) of thelongitudinal extension portion 30 is smaller than the thickness of thefirst contact portion 29, and is, for example, 0.05 μm to 0.25 μm.

The second contact portion 31 is formed in the region surrounded by theouter peripheral sides of the source trench 13. In the present preferredembodiment, the source trench 13 has a shape defined by only the outerperipheral sides in a plan view, and the second contact portion 31 isselectively formed at the central part of the bottom surface 22 of thesource trench 13. The second contact portion 31 is formed so as to havea size large enough to straddle the inside and outside of theinsulating-film residue 24. The thickness (depth in the longitudinaldirection from the bottom surface 22 of the source trench 13) of thesecond contact portion 31 is 0.1 μm to 0.3 μm. This thickness is smallerthan the thickness of the p type region 27, and therefore the secondcontact portion 31 is formed in a state of floating to a surface part ofthe p type region 27. The second contact portion 31 is formed in the ptype region 27, and, as a result, it is possible to reduce the sheetresistance of the p type region 27 of a bottom part of the source trench13. Therefore, it is possible to reduce the resistance of a body diodeformed by the pn junction between the p type region 27 and the n⁻ typedrain region 26.

An interlayer film 32 is formed on the SiC substrate 2 so as to coverthe gate electrode 20. The interlayer film 32 is made of, for example,an insulating material, such as silicon oxide (SiO₂). A contact hole 33larger in diameter than the source trench 13 is formed in the interlayerfilm 32. As a result, the n⁺ type source region 11, the first contactportion 29, and the second contact portion 31 of each unit cell 10 areexposed in the contact hole 33.

The source electrode 5 is formed on the interlayer film 32. The sourceelectrode 5 is connected to the n⁺ type source region 11, to the firstcontact portion 29, and to the second contact portion 31 together in thecontact hole 33. The source electrode 5 has a layered structureconsisting of a barrier layer 34 and a metal layer 35. The barrier layer34 is stacked on the interlayer film 32, and the metal layer 35 isformed thereon. The barrier layer 34 is made of, for example,titanium/titanium nitride (Ti/TiN), and the metal layer 35 is made of,for example, aluminum (Al) or an aluminum-copper alloy (Al—Cu).

A drain electrode 36 is formed at a reverse surface of the SiC substrate2. The drain electrode 36 is an electrode shared among all unit cells10. The drain electrode 36 has a layered structure consisting of a metalsilicide layer 37 and a metal layer 38. The metal silicide layer 37 isstacked on the SiC substrate 2, and the metal layer 38 is formedthereon. The metal silicide layer 37 is made of, for example, nickel(Ni) silicide, titanium (Ti) silicide, or the like, and the metal layer38 is made of, for example, aluminum (Al) or an aluminum-copper alloy(Al—Cu).

FIG. 3 is a flowchart to describe a method for manufacturing thesemiconductor device 1.

In order to manufacture the semiconductor device 1, first, a SiC crystalis grown on the base substrate 14 while being doped with an n typeimpurity (for example, N (nitrogen), P (phosphorus), As (arsenic), orthe like) according to an epitaxial growth method, such as a CVD method,an LPE method, or an MBE method (step S1). As a result, the n typeactive layer 15 is formed on the base substrate 14.

Thereafter, a p type impurity (for example, Al (aluminum), B (boron), orthe like) is implanted into the n⁻ type active layer 15. Thereafter, ann type impurity is implanted into the n⁻ type active layer 15.Thereafter, the SiC substrate 2 is annealed at, for example, 1400° C. to2000° C. (step S2). As a result, the p type impurity and the n typeimpurity that have been implanted into the n⁻ type active layer 15 areactivated, and the p type channel region 12 and the n⁺ type sourceregion 11 are simultaneously formed in accordance with places into whichthose impurities have been implanted. Additionally, the n⁻ type drainregion 26 that maintains the state of the n⁻ type active layer 15 thathas already made epitaxial growth is formed at a lower part of the ptype channel region 12.

Next, the gate trench 9 and the source trench 13 are formed (step S3).The SiC substrate 2 is etched by use of a mask that has an opening in aregion in which the gate trench 9 and the source trench 13 are to beformed. As a result, the SiC substrate 2 undergoes dry etching from itsfront surface, and the gate trench 9 and the source trench 13 aresimultaneously formed. Simultaneously, many unit cells 10 are formed inthe SiC substrate 2. It is possible to use, for example, a mixed gas(SF₆/O₂ gas) including sulfur hexafluoride (SF₆) and oxygen (O₂) or amixed gas (SF₆/O₂/HBr gas) including SF₆, O₂, and hydrogen bromide (HBr)as an etching gas.

Thereafter, with reference to FIG. 4 in addition to FIG. 3, a mask 39with which the whole area of the SiC substrate 2 excluding the sourcetrench 13 is covered is formed on the SiC substrate 2. In the plan viewof FIG. 4, an outlined part is the opening portion of the mask 39.Thereafter, the p type impurity is implanted toward the source trench 13exposed from the opening portion of the mask 39. The implantation ofthis impurity is performed by diagonal implantation in which theimpurity is allowed to strike in an inclined direction with respect to anormal direction of the front surface of the SiC substrate 2. Theincident angle of the impurity is controlled by, for example, a magneticfield. As a result, the p type impurity is implanted into the entireinner surface of the source trench 13. Thereafter, the SiC substrate 2is annealed at, for example, 1400° C. to 2000° C. (step S4). As aresult, the p type impurity implanted thereinto is activated, and the ptype region 27 is formed.

Thereafter, with reference to FIG. 5 in addition to FIG. 3, a mask 40that selectively exposes the source trench 13 and a part of the n⁺ typesource region 11 is formed on the SiC substrate 2. In the plan view ofFIG. 5, an outlined part is the opening portion of the mask 40.Thereafter, the p type impurity is implanted toward the source trench 13and the n⁺ type source region 11 exposed from the opening portion of themask 40. At this time, the p type impurity is implanted under thecondition that it is higher in dose amount and is lower in energy thanwhen the p type region 27 is formed. Additionally, the implantation ofthis impurity is performed by diagonal implantation in which theimpurity is allowed to strike in an inclined direction with respect tothe normal direction of the front surface of the SiC substrate 2.Thereafter, the SiC substrate 2 is annealed at, for example, 1400° C. to2000° C. (step S5). As a result, the p type impurity implanted thereintois activated, and the p⁺ type channel contact region 28 that integrallyincludes the first contact portion 29, the longitudinal extensionportion 30, and the second contact portion 31 is formed.

Next, the gate insulating film 19 and the gate electrode 20 are formed(step S6). A SiO₂ material is deposited on the SiC substrate 2 accordingto, for example, the CVD method. As a result, the gate insulating film19 is formed. Subsequently, a polysilicon material is deposited on theSiC substrate 2 according to, for example, the CVD method. Thepolysilicon material continues to be deposited at least until the gatetrench 9 and the source trench 13 are completely filled therewith.Thereafter, the polysilicon material is etchbacked until an etchbacksurface becomes flush with the front surface of the SiC substrate 2. Asa result, the gate electrode 20 is formed. At this time, anelectrode-film residue 25 made of a remaining polysilicon material isformed at the source trench 13.

Next, the interlayer film 32 that has the contact hole 33 is formed(step S7). A SiO₂ material is deposited on the SiC substrate 2 accordingto, for example, the CVD method. As a result, the interlayer film 32 isformed. Subsequently, the interlayer film 32 and the gate insulatingfilm 19 continuously undergo patterning. As a result, the contact hole33 that passes through the interlayer film 32 and through the gateinsulating film 19 is formed. At this time, in the source trench 13, apart of the gate insulating film 19 remains as the insulating-filmresidue 24 at a part sandwiched between the electrode-film residue 25and the inner surface of the source trench 13.

Thereafter, the source electrode 5, the drain electrode 36, etc. areformed (step S8), and, as a result, the semiconductor device 1 shown inFIG. 2 is obtained.

According to the semiconductor device 1, it is possible to use the firstcontact portion 29 and the longitudinal extension portion 30 as anelectric-charge path to the p type channel region 12. Additionally, thep⁺ type channel contact region 28 is formed according to diagonalimplantation under the condition that it is higher in dose amount and islower in energy than when the p type region 27 is formed. This makes itpossible to also efficiently implant the impurity into the side surface21 of the source trench 13 in which an impurity-implantation amount isliable to become smaller than in the front surface of the SiC substrate2 or in the bottom surface 22 of the source trench 13, and makes itpossible to form the longitudinal extension portion 30 along the sidesurface 21 of the source trench 13 without disconnection. On the otherhand, although the p type region 27 is formed according to diagonalimplantation, there is a case in which disconnection occurs particularlyin the side surface 21 of the source trench 13 because it has a widerrange and a smaller dose amount than the p⁺ type channel contact region28. However, in the semiconductor device 1, it is possible to reliablymake contact with the p type channel region 12 by means of the p⁺ typechannel contact region 28 even if disconnection occurs in the p typeregion 27. Additionally, it is possible to restrain variation in gatethreshold voltage by using the p⁺ type channel contact region 28 that islower in resistance than the p type region 27 as an electric-chargepath. As a result, it is possible to restrain variation in ΔVth betweenchips in a semiconductor wafer plane, and therefore, if a module isformed by use of a plurality of chips that are individual pieces createdfrom a semiconductor wafer in which the structure of the semiconductordevice 1 has been employed, it is possible to reduce a switching timelag in the module.

Additionally, the first contact portion 29 is formed so as to extendfrom the four sides of the source trench 13 in different fourdirections. Therefore, for example, even if the mask 40 positionallydeviates downwardly in the sheet of the drawing so that the formationregion of one first contact portion 29 is covered with the mask 40 whenthe mask 40 of FIG. 5 is formed, it is possible to reliably expose theformation regions of the remaining three first contact portions 29.Therefore, it is possible to reliably format least three first contactportions 29. It is possible to achieve this effect, for example, evenwhen the first contact portion 29 extends only in different twodirections along the left-right direction of the drawing sheet. In otherwords, it is possible to reliably form at least right-hand first contactportions 29 placed on the right side of the drawing sheet even if themask 40 positionally deviates in the left-right direction of the drawingsheet.

FIG. 6 is a view showing one preferred embodiment of the semiconductordevice 1 in detail, in which the source trench 13 has the secondpattern. In FIG. 6, the same reference sign is given to a componentcorresponding to each component shown in FIGS. 1 to 5 mentioned above,and a description of this component is omitted.

In FIG. 6, the source trench 13 is formed in a quadrangular ring shapein a plan view. As a result, a convex portion 41 (mesa portion) definedby inner peripheral sides of the source trench 13 is formed in an innerregion of the source trench 13. Additionally, the source trench 13 hasthe same depth and width as the gate trench 9.

The p type region 27 is formed at an outer edge part of the sourcetrench 13 and in the whole of its inner region in the same way as thearrangement of FIG. 2. Therefore, the p type region 27 has an outersurface that extends from the p type channel region 12 in thelongitudinal direction along the side surface 21 and that extends in thelateral direction along the bottom surface 22, and, in addition, has anouter surface that extends in the lateral direction along the frontsurface of the SiC substrate 2 below the convex portion 41. As a result,the semiconductor device 1 of FIG. 6 has the p type region 27 formeddeeper than the source trench 13 below the convex portion 41. In thepresent preferred embodiment, the convex portion 41 has its most partsconsisting of the p type region 27, which exclude its surface part.

With respect to the p⁺ type channel contact region 28, the secondcontact portion 31 is formed at the whole of the surface part of theconvex portion 41. The longitudinal extension portion 30 is formed so asto come around through the bottom part of the source trench 13 from theouter edge part to the inner edge part of the source trench 13. It isconnected to the first contact portion 29 at the outer edge partthereof, and is connected to the second contact portion 31 at the inneredge part thereof. In other words, the longitudinal extension portion 30includes parts that are formed at the side part and the bottom part onthe outer side of the source trench 13 and that are formed at the sidepart on the inner side of the source trench 13 in a side portion (crosssection A-A) of the source trench 13. Additionally, the longitudinalextension portion 30 includes parts that are not formed at the side partand the bottom part on the outer side of the source trench 13 and thatare selectively formed at the side part on the inner side of the sourcetrench 13 in a corner portion (cross section B-B) of the source trench13.

The insulating-film residue 24 is formed at the entire inner surface ofthe source trench 13, and the electrode-film residue 25 is embedded inthe inside thereof. In other words, in a cross-sectional view, theinsulating-film residue 24 and the electrode-film residue 25 have thesame arrangement as the gate insulating film 19 and the gate electrode20, except that those residues are not covered with the interlayer film32.

Each of the other arrangements is the same as that of FIG. 2. It ispossible to fulfill the same operation and effect by the arrangement ofFIG. 6 as by the arrangement of FIG. 2.

In order to form the p type region 27 of FIG. 6, it is recommend to usea mask 42 with which the whole area of the n⁺ type source region 11excluding both the source trench 13 and the convex portion 41 is coveredas shown in FIG. 7 when a p type impurity is implanted. Additionally, inorder to form the p⁺ type channel contact region 28 of FIG. 6, it isrecommended to use a mask 43 by which the whole of the convex portion 41is exposed and by which the source trench 13 and a part of the n+ typesource region 11 are selectively exposed as shown in FIG. 8 when a ptype impurity is implanted.

Although the preferred embodiment of the present invention has beendescribed as above, the present invention can be embodied in othermodes.

For example, as shown in FIG. 9, the gate trench 9 may be formed in astripe manner, and two stripe-shaped source trenches 13 may be formedbetween the gate trenches 9. As a result, a repeated pattern of aline-and-space shape may be formed by the gate trench 9 and the sourcetrench 13. A convex portion 44 (stripe mesa portion) defined by theinner peripheral sides of the source trench 13 is formed between the twosource trenches 13. The second contact portion 31 may be formed at thesurface part of the convex portion 44, of course, in the same way as inFIG. 6.

Additionally, as shown in FIG. 10, the gate trench 9 may be formed in ahoneycomb manner, and, as a result, a repeated pattern of a regularhexagonal unit cell 10 may be formed. In this case, the source trench 13may have a regular hexagonal shape or a regular hexagonal ring shape ina plan view.

Additionally, for example, the longitudinal extension portion 30 is notrequired to be exposed to the inner surface of the source trench 13 ifthe p⁺ type channel contact region 28 is formed such that the firstcontact portion 29 is able to make contact with the front surface of theSiC substrate 2. In other words, the first contact portion 29 is notnecessarily required to be formed at the peripheral edge part of thesource trench 13, and can be formed at an arbitrary position of the n⁺type source region 11.

Additionally, the second contact portion 31 that has a longer distancefrom the p type channel region 12 than the first contact portion 29 canalso be excluded if necessary.

Additionally, an arrangement in which the conductivity type of eachsemiconductor part of the aforementioned semiconductor device 1 has beenreversed may be employed. For example, in the semiconductor device 1,the p type part may be an n type part, and the n type part may be a ptype part.

Additionally, a semiconductor employed in the semiconductor device 1 isnot limited to SiC, and may be, for example, Si, GaN, diamond, or thelike.

Besides, various design changes can be made within the scope of thesubject matter recited in the claims.

The present application corresponds to Japanese Patent Application No.2014-233653 filed in the Japan Patent Office on Nov. 18, 2014, and theentire disclosure of the application is incorporated herein byreference.

Preferred Embodiment

In order to prove the effect of the aforementioned preferred embodiment,variation in ΔVth was verified with respect to a semiconductor wafer 45that employs an improved structure of the semiconductor device 1 and asemiconductor wafer 46 that does not employ an improved structure of thesemiconductor device 1 as shown in FIG. 11. In the latter structure, thep⁺ type channel contact region 28 consisting of only the second contactportion 31 was formed without forming the first contact portion 29 andthe longitudinal extension portion 30.

As shown in FIG. 11, in the semiconductor wafer 46 that does not employthe improved structure, chips 47 (hatched chips) of ΔVth=0.9 V weredistributed chiefly at a wafer peripheral edge part, whereas chips 48(outlined chips) of ΔVth=0.5 V to 0.6 V were roughly distributed in theother regions. In other words, in the semiconductor wafer 46, variationin ΔVth between chips in a wafer plane was remarkable. On the otherhand, in the semiconductor wafer 45 that employs the improved structure,chips 48 of ΔVth=0.5 V to 0.6 V were distributed in most regions, andvariation in ΔVth was small.

REFERENCE SIGNS LIST

-   -   1 Semiconductor device    -   2 SiC substrate    -   5 Source electrode    -   9 Gate trench    -   11 n⁺ type source region    -   12 p type channel region    -   13 Source trench    -   16 (Gate trench) Side surface    -   17 (Gate trench) Bottom surface    -   18 (Gate trench) Corner portion    -   21 (Source trench) Side surface    -   22 (Source trench) Bottom surface    -   23 (Source trench) Corner portion    -   25 Electrode-film residue    -   27 p type region    -   28 p⁺ type channel contact region    -   29 First contact portion    -   30 Longitudinal extension portion    -   31 Second contact portion    -   39 Mask    -   40 Mask    -   41 Convex portion    -   42 Mask    -   43 Mask    -   44 Convex portion

1. A semiconductor device comprising: a semiconductor layer; a gatetrench that defines a source region of a first conductivity type in thesemiconductor layer; a channel region of a second conductivity type of alower part of the source region; a source trench that passes through thesource region and the channel region; an impurity region of the secondconductivity type of a bottom part and a side part of the source trench;a source electrode on the semiconductor layer; and a highly-concentratedimpurity region of the second conductivity type, the highly-concentratedimpurity region having a contact portion connected to the sourceelectrode at a surface of the semiconductor layer, thehighly-concentrated impurity region passing through the source regionand extending to a position deeper than the source region, thehighly-concentrated impurity region having a concentration higher thanthe impurity region.
 2. The semiconductor device according to claim 1,wherein the source trench is formed as a single source trench in acutting plane that appears when the semiconductor layer is cut in adirection of a depth of the source trench.
 3. The semiconductor deviceaccording to claim 1, wherein the source trench is formed as two sourcetrenches in a cutting plane that appears when the semiconductor layer iscut in a direction of a depth of the source trench.
 4. The semiconductordevice according to claim 1, wherein the highly-concentrated impurityregion is formed apart from a channel portion located on a side surfaceof the gate trench.
 5. The semiconductor device according to claim 4,wherein the highly-concentrated impurity region is formed along a sidesurface of the source trench.
 6. The semiconductor device according toclaim 1, wherein the highly-concentrated impurity region is formed so asto extend to a bottom surface of the source trench.
 7. The semiconductordevice according to claim 1, wherein the contact portion is selectivelyformed at a part of the source region.
 8. The semiconductor deviceaccording to claim 1, wherein the highly-concentrated impurity region isformed along an inner surface of the source trench so as to extend to abottom surface of the source trench, and the contact portion isselectively formed at a part of the source region.
 9. The semiconductordevice according to claim 1, wherein the contact portion is formed so asto extend in at least two directions from an upper side of the sourcetrench.
 10. The semiconductor device according to claim 9, wherein thegate trench is formed in a grid-shaped manner, and the source trench isformed in a quadrangular shape or a quadrangular ring shape in a planview in an inner region of the gate trench formed in the grid-shapedmanner, and the contact portion is formed so as to extend outwardly fromfour sides of the source trench.
 11. The semiconductor device accordingto claim 1, wherein a repeated pattern of a line-and-space shape isformed by the gate trench and the source trench.
 12. The semiconductordevice according to claim 1, wherein a repeated pattern of a hexagon isformed by the gate trench.
 13. The semiconductor device according toclaim 1, further comprising an electrode-film residue disposed at aperipheral part of the bottom part of the source trench, wherein thehighly-concentrated impurity region includes a second contact portionformed at a part of the bottom part of the source trench.
 14. Thesemiconductor device according to claim 13, wherein the electrode-filmresidue is formed so as to selectively cover a peripheral edge part ofthe second contact portion.
 15. The semiconductor device according toclaim 1, further comprising an electrode-film residue disposed in thesource trench, wherein the highly-concentrated impurity region includesa second contact portion formed at at-least one part of a peripheralpart of the source trench.
 16. The semiconductor device according toclaim 15, further comprising a convex portion formed in an inner regionof the source trench formed in a ring shape, wherein the second contactportion is formed at a surface part of the convex portion.
 17. Thesemiconductor device according to claim 15, further comprising a convexportion formed between the source trench and the source trench both ofwhich are adjacent to each other and each of which is formed in a stripemanner, wherein the second contact portion is formed at a surface partof the convex portion.
 18. The semiconductor device according to claim15, wherein the electrode-film residue is embedded in the source trench.19. The semiconductor device according to claim 1, wherein the sourcetrench has a depth equal to a depth of the gate trench, and, meanwhile,has a width greater than a width of the gate trench.
 20. A method formanufacturing a semiconductor device, the method comprising: a step offorming a source region of a first conductivity type and a channelregion of a second conductivity type in order from a surface of asemiconductor layer; a step of forming a gate trench that defines thesource region so as to have a predetermined shape and a source trenchlocated in the source region; a step of forming an impurity region at abottom part and a side part of the source trench by implanting animpurity of the second conductivity type into the source trench in astate in which a surface of the source region is masked; and a step offorming a highly-concentrated impurity region by implanting an impurityof the second conductivity type in a state in which the surface of thesource region is partially masked, the highly-concentrated impurityregion passing through the source region and extending to a positiondeeper than the source region, the highly-concentrated impurity regionhaving a concentration higher than the impurity region.
 21. The methodfor manufacturing a semiconductor device according to claim 20, whereinthe step of forming the highly-concentrated impurity region includes astep of diagonally implanting the impurity of the second conductivitytype into a side surface of the source trench by use of a mask thatexposes an inside of the source trench.
 22. The method for manufacturinga semiconductor device according to claim 21, wherein the step offorming the highly-concentrated impurity region includes a step ofimplanting an impurity under a condition of being higher in dose amountand lower in energy than when the impurity region is formed.